Writing Reusable VHDL Code using Generics and Generate Statements
VHDL: Convert a Fixed Module into a Generic Module for Reuse - Blog - FPGA - element14 Community
Incomplete Port Maps and Generic Maps - Sigasi
Reconfigurable Computing - VHDL – Signals, Generics, etc John Morris The University of Auckland Iolanthe 'on the hard' at South of Perth Yacht Club. - ppt download
VHDL basics _02.1, from Altera - YouTube
3.8.16 Use Component Auto Instance
Generic Constant - an overview | ScienceDirect Topics
How to use Port Map instantiation in VHDL - VHDLwhiz
Generics in VHDL - Nandland
Structure of VHDL Code Digital Design using VHDL - Care4you